1. Field of the Invention
The present invention relates to a semiconductor memory system including a semiconductor memory device such as a cache memory for outputting data upon reception of an address from a CPU and, more particularly, to a highly-efficient, high-speed semiconductor memory system wherein a CPU monitors a signal which is generated in synchronization with data output from a memory and represents that the output data is valid and controls a cycle of operations for reading data from the memory to thereby reduce a wait of the CPU.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional semiconductor memory system using a CPU (Central Processing Unit). In this system, a memory control chip 42 is connected to a CPU chip 41, and a plurality of memory chips 43 are connected to the memory control chip 42 through a bus for transmitting addressing signals, data, control signals, and the like. FIG. 2 is a block diagram showing another conventional semiconductor memory system using a CPU. In this system, a CPU 41 is directly connected to a plurality of memory chips 43.
Memories are generally essential for configuring a semiconductor memory system using a CPU. In order to enhance the efficiency of the system, usually, a number of memory chips serving as secondary cache memories are arranged in addition to a CPU chip on which a small-sized memory such as a register or a cache memory is mounted. In the system shown in FIG. 1, the memory control chip 42 for controlling a memory such as a cache controller is disposed between the CPU 41 and the memory chips 43, and the CPU chip 41 and memory control chip 42 are connected by wiring on a substrate as are the memory control chip 42 and the memory chips 43. As shown in FIG. 2, there has recently been a method of directly connecting the memory chips 43 to the CPU chip 41 having a function of the memory control chip in order to heighten the efficiency of the system further. In the system shown in FIG. 2, the time for one cycle of the CPU which allows the memory to perform a reading operation corresponds to the time required from when the CPU outputs an addressing signal until the memory outputs data to the data bus in response to the addressing signal and until the CPU receives the data. The shortest cycle time of the CPU depends upon the capacity thereof, and the memory allows high-speed access so that the reading operation can be performed within the cycle time.
As the efficiency of the system is improved and the shortest cycle time of the CPU is reduced, a delay in access due to the wiring of an address bus or a data bus increases. It is thus necessary to increase the speed of memory access more than that of the CPU. Since, however, there is a limit to the speed of memory access, a considerably high-speed memory cannot be provided for a CPU of the same generation. For this reason, the reading operation cannot be performed within the shortest cycle time, and a wait is necessary for the CPU, resulting in the degradation of the efficiency of the entire system. This problem becomes more serious as the delay due to wiring, which is proportionate to the length of the wiring, increases. In other words, the larger the size of the memory, the longer the length of the wiring, thus causing a decrease in the efficiency of the system. There is a difference in time required for the reading operation, which corresponds to a difference in delay due to wiring, between a memory chip near the CPU and a memory chip far from the CPU, and the cycle time of the CPU is determined by the access time of the farthest memory chip. The delay due to wiring is chiefly caused by a parasitic inductance and, thus, it is very difficult to correctly obtain the exact amount of time involved in the delay in the system. Therefore, the reading operation cannot be completed within the cycle time of the CPU, the failure of which should be avoided in order to prevent the system from malfunctioning.
As described above, the conventional semiconductor memory system has the following drawback: If the efficiency of the CPU is heightened, then a delay due to wiring occurs in the memory. The cycle time of the CPU can be shortened only to such an extent that the delay does not cause the system to malfunction. Therefore, the efficiency of the system cannot be enhanced greatly.